Today ICs are designed to include test circuitry, such as scan and Built In Self Test (BIST), that can be used to test the IC at all levels of assembly and manufacturing, i.e. wafer test, packaged IC test, system integration test, and field test. In order to reuse the test circuitry in such a manner, the test circuitry must be designed as an integral and active part of the IC. Being an integral part of the IC, the test circuitry is connected to the functional circuitry to be tested and also connected to the IC power supply rails.
While this is the way traditional test circuitry is designed into ICs, there are some types of specialized test circuitry included in ICs that only participate in wafer level testing. This specialized test circuitry advantageously allows wafer level testing to be performed using lower cost testers and with higher precision, especially the testing of sensitive analog circuits. Like other scan and BIST test circuitry, this specialized test circuitry is conventionally designed to be connected to the functional circuitry it will test and to the IC's power supplies. However, unlike the scan and BIST circuitry, the specialized test circuitry is only usable at the wafer test level since the die pads required for accessing the specialized test circuitry are typically not bonded out to package pins.
U.S. Pat. No. 5,578,935 teaches a method and apparatus of testing a circuit under test by embedding an integrated strobed comparator test circuit in the IC and connecting an input of the comparator to the output of a circuit under test in the IC. The integrated strobed comparator and circuit under test are also connected to an external tester for power, reference voltage inputs, and test input stimulus and output response signaling. The test arrangement of FIG. 1 of U.S. Pat. No. 5,578,935 allows the tester, the circuit under test and comparator within the IC to interact together according to a described successive approximation algorithm of FIG. 2 to achieve the test. The motivation and advantages for embedding the comparator into the IC are that the embedded comparator minimizes the effect of stray capacitance and inductance on a signal under test.